Accompanying improvement in performance of information processing equipment such as apparatuses and servers for communication backbone, it is necessary to improve information processing speed in devices or semiconductor chips. Further, to avoid a problem of heating, it is necessary to lower power consumption per performance at the same time as speed improvement. In a synchronous circuit, a considerable portion (several tens of percent) of power consumption is spent for clock signals. Reducing delays of logic circuits sufficiently for satisfying timing conditions also leads to increase in power consumption. As a method for solving these problems, there is an asynchronous logic method which performs a logical operation only when preparation of necessary data is completed. In an asynchronous logic circuit, a logical operation is performed after waiting until all inputs become valid, and completion of the logical operation is notified to the input side by returning a completion signal. In the asynchronous circuit, it is unnecessary to distribute clock signals for synchronization to the entire semiconductor chip, and it is also unnecessary for all logical operations to complete within a clock cycle. Thus, the asynchronous circuit can achieve low power consumption compared to the synchronous circuit.
Further, there is known an asynchronous data transmission system such that, in a transmission system performing asynchronous/synchronous speed conversion upon reception of asynchronous data from a terminal apparatus and performing synchronous data communication on a transmission path, there is provided means for writing asynchronous data of a transmission terminal apparatus to an FIFO memory at an asynchronous data transmission speed on the transmitting side, and a transmission operation to a transmission terminal apparatus is suspended when the FIFO memory overflows during writing by the writing means, thereby turning to an idle state (see, for example, Patent Literature 1).
Further, there is known a communication apparatus receiving data transmitted from another communication apparatus, the communication apparatus including receiving means for receiving data, first packet generating means for generating an acknowledge packet indicating contents of response to the other communication apparatus with respect to data received by the receiving means and transmitting the acknowledge packet to the other communication apparatus, and second packet generating means for generating a data request packet requesting transmission of data to the other communication apparatus regardless of the result of reception of data by the receiving means and transmitting the data request packet to the other communication apparatus (see, for example, Patent Literature 2).
[Patent Literature 1] Japanese Laid-open Patent Publication No. 8-172426
[Patent Literature 2] Internal Publication Pamphlet No. WO2007/043373
In modern information processing apparatuses, achievement of both reduction in power consumption and improvement in processing performance is a large problem. One effective method to reduce power consumption is to perform asynchronous operation such that circuits are operated only when necessary. Various methods are known for performing asynchronous operation inside a semiconductor chip. In a typical asynchronous logic circuit, a request signal is asserted when the circuit turns to a state capable of processing input data, and a completion signal is asserted when a signal is processed and the circuit becomes capable of accepting the next signal input. By such an asynchronous method, it becomes possible to reduce power consumption because the logic circuit operates only when processing is needed.
When the scale of the asynchronous logic circuit becomes large, it is necessary to make a logic circuit across plural semiconductor chips. In this case, if a typical asynchronous method similar to that in a semiconductor chip is used for exchanging signals between the semiconductor chips, there occurs a problem that the data rate of communication between the semiconductor chips decreases significantly. This is because when a valid signal is passed from a transmitting side to a receiving side, and the receiving side processes the signal and returns a completion signal, the time of the sum of a delay in a transmission path and a delay in a transceiver in amount of a round trip is needed at the minimum. This decreases the data rate to a fraction of that of a typical fast I/O. This problem exists not only in communication between semiconductor chips but also when signal transmission via a long distance with a large signal delay is performed inside a semiconductor chip.
Further, accompanying improvement in processing performance of semiconductor chips, what is called a fast I/O using serial transmission is used for signal communication between semiconductor chips. However, there exists a problem that there is no power consumption effect by the asynchronous operation because an internal circuit operates at high speed in a typical fast I/O even when it does not perform transmission/reception.